Implementing a phase-locked loop is common for controlling a frequency in an electronic circuit. Then, the frequency can be tuned by varying a parameter of the phase-locked loop which results in modifying a time-delay of one of the signals effective within the phase-locked loop.
Such electronic circuits may be frequency generators or switch-mode power supplies, for example.
Switch-mode power supplies such as DC-DC buck converters operate by pulse-width modulation for producing an output signal with desired voltage value. These switch-mode power supplies convert a continuous transfer function into a digital modulation scheme which results in a time-ratio suitable for producing the output voltage value desired.
A sliding-mode modulator converts the continuous transfer function by sign comparison. It provides asynchronous transient response, however the switching frequency itself is not primarily related with this voltage value, so that this frequency remains uncontrolled and may interfere with the operation of other systems. Because of this reason, it is often necessary to clamp or control the switching frequency of a switch-mode power supply, and a phase-locked loop is usually implemented to this purpose.
FIG. 1 is a block diagram of a known DC-DC buck converter used as an example. The reference number 10 generally indicates the converter, and the other reference numbers used in this Figure have the following meanings:                11 hysteresis comparator        12 switching logic and gate drivers unit of the converter, noted S.W.        13 power stage including a pMOS transistor 13a and a nMOS transistor 13b connected in series between terminals of a DC-power supply with supply voltage VIN         14 a low-pass filter including a power inductance 14a and a capacitor 14b         15 an external load charge        16 a feedback line which may use a combination of the current IL in the power inductor 14a and the output voltage VOUT across the load charge 15 as feedback parameter        
In such sliding-mode operating circuit, the feedback line 16 is fed into the negative input terminal of the comparator 11, and a reference voltage VREF is applied to the positive input terminal of the comparator 11. Signal FB which is transmitted by the feedback line 16 becoming higher of less than a reference voltage VREF triggers the comparator 11 to switch, and the switch is propagated to the switching logic unit 12 and the power stage 13.
FIG. 2 is a block diagram of a known phase-locked loop design implemented for controlling the switching frequency of the converter 10 of FIG. 1. The converter 10 appears as a module in this loop, which also comprises a combiner 21 and a filter 22 noted L.P. The combiner 21 is fed with a frequency or phase reference FREF on one hand, and with a switching node VIX which is produced by the converter 10 and contains the switching frequency or phase. In a known manner, for example from document U.S. Pat. No. 6,348,780, the output of the low-pass filter 22 can be connected to a control terminal of the converter 10, suitable for modifying its switching frequency. Thus, tuning the frequency reference FREF allows adjusting the switching frequency of the controller 10. For example, the control terminal of the converter 10 acts by modifying features of the hysteresis cycle of the comparator 11 within the converter 10, such as the threshold values of the hysteresis cycle. But this first design of a tunable phase-locked loop leads to degraded transient behaviour for the converter 10, which is not acceptable for some applications.
Then, in particular for applications which require transient operation performances, it has been proposed to modify the phase-locked loop design by introducing a variable time-delay on the path of the switched signal, for example within the converter 10. Such design is described in particular by Pengfei Li et al. in “A 90-240 Mhz Hysteretic Controlled DC-DC Buck Converter with Digital PLL Frequency Locking”, IEEE Custom Integrated Circuits Conference, pp. 21-24, San Jose, Calif., doi: 10.1109/CICC.2008.4672010. The principle is illustrated schematically in FIG. 3, where a chain of several tunable delay cells 25 is inserted in the path of the switched signal within the converter 10, for example within the switching logic unit 12 of FIG. 1. The total time-delay can be controlled digitally by a dedicated controller 26, noted CTRL. But such other design for a phase-locked loop requires more silicon chip area, and is energy consuming to a significantly higher extent.
Therefore, an object of the present invention is to propose a new design for adjusting a switching frequency, which alleviates the drawbacks of the prior designs.